2. Sleep modes overview

To give an overview of the sleep modes available, the following section will give more idea on each mode and its application.

The block diagram of the DA14531 is as shown below and the highlighted red box is where the retention memory blocks are placed and this includes SysRAM1 (16kB), SysRAM2 (12kB) and SysRAM3 (20kB). So a total of 48kB system RAM is available.


Figure 1 DA14531 Block Diagram

  1. Extended Sleep mode
    • In Extended sleep mode, the system domain except the SysRAM, the radio domain and the peripheral domain are powered down and the XTAL16M clock is stopped. The SysRAM is still powered to retain data but is not accessible.
    • The AON power domain is ON to keep data in the retention RAMs and to supply power to the blocks that can wake the system up, i.e. wakeup timer, quadrature decoder and the BLE timer.
  2. Deep sleep mode
    • In Deep sleep mode, to reduce the power consumption even further, the SysRAM is also powered off. The status of the other power domains is the same as in Extended sleep mode.
    • The device can wake-up from deep sleep either using clocked-wake up controller, from GPIOs, RTC alarm or Timer1.
  3. Hibernation sleep mode
    • In Hibernation mode as compared to previous two sleep modes, the PD_SLP (Sleep power domain) domain is switched off. This means the CRG (Clock and Reset Generator) is powered off and this is why this mode is called Clock-less mode.
    • The device can wake-up from only GPIOs that is configured to wake-up. The available GPIOs to wake the device up from hibernation is P0_1, P0_2 … P0_5.

3. Sleep modes hardware overview

Sleep modes are configured by #defines in the SDK. However, this section explains the hardware power domains and how these are configured in each of the sleep modes. The sleep mode in general has no power gating programmed. The ARM CPU is idle and waiting for an interrupt, PD_SYS is on whereas PD_TIM and PD_RAD depend on the programmed enabled value.

To know which power domain powers what part of the blocks, refer to the below figure on mapping of digital power domains and blocks,


Figure 2 DA14531 Mapping of Digital Power Domains and Blocks

For example, the PD_SYS powers up the SysRAM blocks as seen in the figure above.

  • AMBA AHB (Advanced Micro controller Bus Architecture, Advanced High-performance Bus)- DA14531 is based on this, and is used to connect components that need high bandwidth.
  • DMA Engine (Direct memory Access) - connected to AHB bus as master and has the highest priority to copy code from OTP into SysRAM.
  • CRG - Clock and Reset Generator - This block is responsible for generating the clock signals and system reset.
  • WIC - Wake-up Interrupt Controller - to allow the processor to be powered down during sleep, while interrupt sources are still allowed to wake up the system

The description of the power domain is mentioned in the table below,

Table 1 Power Domains Description
Domain Name Description
PD_AON Always powered domain. It contains a Clock-less Wake Up controller and the pad-ring.
PD_SLP Sleep power domain. It comprises of the ARM/WIC (Wake-up Interrupt controller, the BLE Timer, the PMU/CRG, the Clocked Wakeup Controller, the Quadrature Decoder, and various registers required for the Wake-Up sequence.
PD_SYS System Power Domain. It comprises of the AHB bus, the OTP cell and controllers, the ROM, the System RAM, the Watchdog, the SW Timer, and the GPIO port multiplexing.
PD_TIM Timer Power Domain. It comprises of the RTC and the Timer1. These two blocks can be active during the sleep modes.
PD_RAD Radio Power Domain. It comprises of the BLE Core and the digital PHY of the Radio.

The above mentioned are the different power domains in the chip that can be enabled/disabled individually in each of the power saving modes.

For further details, refer to the datasheet section, for more extensive content on the same.

The DA14531 has 3 sleep modes available:

  1. Extended sleep mode: PD_AON, PD_SLP, and conditionally PD_TIM are active. RAM is expected to be retained for:
    • Keeping a BLE connection alive (stack variables or BLE data)
    • Potentially keep the application code and it can be omitted if the OTP (One-Time Programmable) is instructed to automatically get mirrored into RAM upon every wake up
  2. Deep Sleep mode: Shipping clocked mode with all domains is disabled. RAM may or may not be retained. RTC ticking is programmable.
  3. Hibernation mode: Shipping clock-less mode with all domains is disabled. RAM may or may not be retained. No clock is running.

A summary of the power modes, the digital power domains, as well as the clocks and wake-up capabilities are explained in Figure 1 below.


Figure 3 Power Modes, Digital Power Domains, Clocks, and Wake-up triggers

3.1. Hardware Setup

This example runs on the BLE Smart SoC (System on Chip) devices: - DA14531 daughter board + DA145xxDEVKT-P PRO-Motherboard.

The user manuals for the development kits can be found here.

The figure below shows the hardware setup for the SPI Flash.


Figure 4 Hardware setup with SPI Flash and jtag jumpers placed

If you want to run the firmware from SysRAM or OTP, the SPI related jumpers can be taken off.


Figure 5 Hardware setup with jtag jumpers placed

To run the device in Boost mode, re-arrange the jumper J4 to J4[1-2] on the motherboard and use the switch to position itself to L, as shown in the picture below.


Figure 6 Hardware setup with jtag jumpers and boost mode